Logic synthesis using computers has become the standard technique for the design of large scale sequential integrated circuits, which are circuits that include combinational subcircuits separated by storage or memory elements, such as clocked flip-flops and registers, also known as latches.
It is often the case that sequential circuits, as initially synthesized by CAD tools, include combinational subcircuits that with redesign can be operated with shorter clock periods, a factor that is normally desirable. There have been various ongoing efforts to devise techniques for the redesign of sequential integrated circuits to reduce the clock period at which they can operate and retiming has been an important one of these techniques. Retiming generally revolves repositioning of the flip-flops in the circuit, typically to reduce the length of the longest combinational subcircuits at the expense of adding to the length of shorter combinational subcircuits. In some cases, resynthesis of the combinational subcircuits can also result in a faster integrated circuit. A combination of retiming and synthesis usually results in shorter clock periods that may not be achievable using only one of these techniques.